The present invention relates to insulated-gate field-effect transistor integrated delay lines for digital signals comprising inverters connected in series with respect to the signal flow. The underlying principle of such a delay line is disclosed in the published patent application EP-A-59 802 (ITT case W. Gollinger et al 14-13-12-9-3-2, corresponding to U.S. Pat. No. 4,489,342). The time delay is made adjustable in equidistant steps by providing that the output of every second invert can be taken off via a one-out-of-n selector switch.